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家里的电视盒子不够了，网上买了一个外贸盒子配置如下 晶晨s905 x4 4+32 千兆网口 usb3.0+usb2.0 蓝牙4.0 wifi5GHz/2.4g
到手后发现有点热，拆开换个散热片，结果把内存颗粒碰坏了
上面数第三颗，坏了一个角
于是网上买了一颗一样的颗粒镁光d9tgg，买盒子的时候页面写的DDR3，实际是DDR4给了我一个小惊喜
换好的样子，顺便再拍几张，大家可以看下
换好后插电还是没有视频输出，接上ttl可以跑码
跑码信息如下，大家给看看是哪里的问题
[2022-02-25 11:03:02.842]
RX：SC2:BL:fb9e82;ID:00566015C131152A;FEAT:30F:1FFE0000:B002F:1;POC:FF;RCY:0;OVD:0;DFU:0;eMMC:0;RD-0:0;CHK:0;RVK-N:8000;RVK-C:8000;RVK-A:800;RVK-C:8800;RVK-A:800;RVK-C:8800;RVK-N:8000;RVK-C:8800;SCS:0;RVK-N:00004000;RVK-C:0000c800;RVK-N:00002000;RVK-C:0000e800;
build in ddr magic:ddr4
OTP_LIC00 : 0f0300000000fe1f2f000b0000000000
OTP_LIC10 : 00820700aa01fe00ff00001f00400300
OTP_LIC20 : ffffffbf00000000c280000000000001
OTP_LIC30 : 000000f201000000ff0200f207000000
TE: 186471
BL2 Built : 20:42:11, Aug 9 2021. sc2 griscure-review-sc2-bl2-08032020-120-g922477b - jenkins@walle02-sh
Board ID = 1
Set sys clock to 24Mhz
gp1pll is 1200Mhz. Locked
syspll is 1512Mhz. Locked
Set sys clock to 167Mhz
hifipll is 1800Mhz. Locked
bl2_platform_setup
boot area list:
1STBLOB 00000200 00040000
BL2E 00040200 00013000
BL2X 00053200 00011000
DDRFIP 00064200 00040000
DEVFIP 000a4200 00300000
s_setup from rom:00010081
dma mode
DDR driver_vesion: LPDDR4_PHY_V_0_1_23 build time: Aug 9 2021 20:42:05
ddr clk to 672MHz
ddr fw flag:1
fw_type:1, cfg max:3, mask:0007
try next fw type:0
fw_type:0, cfg max:3, mask:0007
DDR3 probe
ddr clk to 672MHz
Load: DDRFIP From: eMMC - 3.0 src: 00000000, dst: f700ab90, size: 00009600sdemmc src: ;
Check phy result
dram_init
read enable training
fine write leveling
Training has failed!
1D training failed
fw_type:0, cfg max:3, mask:0006
DDR3 probe
ddr clk to 672MHz
Check phy result
dram_init
read enable training
fine write leveling
Training has failed!
1D training failed
fw_type:0, cfg max:3, mask:0004
DDR3 probe
ddr clk to 672MHz
Check phy result
dram_init
read enable training
fine write leveling
Training has failed!
1D training failed
fw_type:0, cfg max:3, mask:0000
All ddr config checked...
boot times 0DDR RST
RST 0xf70260f4
SC2:BL:fb9e82;ID:00566015C131152A;FEAT:30F:1FFE0000:B002F:1;POC:FF;RCY:0;OVD:0;DFU:0;eMMC:0;RD-1:0;CHK:0;RVK-N:8000;RVK-C:8000;RVK-A:800;RVK-C:8800;RVK-A:800;RVK-C:8800;RVK-N:8000;RVK-C:8800;SCS:0;RVK-N:00004000;RVK-C:0000c800;RVK-N:00002000;RVK-C:0000e800;
build in ddr magic:ddr4
OTP_LIC00 : 0f0300000000fe1f2f000b0000000000
OTP_LIC10 : 00820700aa01fe00ff00001f00400300
OTP_LIC20 : ffffffbf00000000c280000000000001
OTP_LIC30 : 000000f201000000ff0200f207000000
TE: 138452
BL2 Built : 20:42:11, Aug 9 2021. sc2 griscure-review-sc2-bl2-08032020-120-g922477b - jenkins@walle02-sh
Board ID = 1
Set sys clock to 24Mhz
gp1pll is 1200Mhz. Locked
syspll is 1512Mhz. Locked
Set sys clock to 167Mhz
hifipll is 1800Mhz. Locked
bl2_platform_setup
boot area list:
1STBLOB 00000200 00040000
BL2E 00040200 00013000
BL2X 00053200 00011000
DDRFIP 00064200 00040000
DEVFIP 000a4200 00300000
s_setup from rom:00010081
dma mode
DDR driver_vesion: LPDDR4_PHY_V_0_1_23 build time: Aug 9 2021 20:42:05
ddr clk to 672MHz
ddr fw flag:1
fw_type:1, cfg max:3, mask:0007
try next fw type:0
fw_type:0, cfg max:3, mask:0007
DDR3 probe
ddr clk to 672MHz
Load: DDRFIP From: eMMC - 3.1 src: 00000000, dst: f700ab90, size: 00009600sdemmc src: ;
Check phy result
dram_init
read enable training
fine write leveling
Training has failed!
1D training failed
fw_type:0, cfg max:3, mask:0006
DDR3 probe
ddr clk to 672MHz
Check phy result
dram_init
read enable training
fine write leveling
Training has failed!
1D training failed
fw_type:0, cfg max:3, mask:0004
DDR3 probe
ddr clk to 672MHz
Check phy result
dram_init
read enable training
fine write leveling
Training has failed!
1D training failed
fw_type:0, cfg max:3, mask:0000
All ddr config checked...
boot times 0DDR RST
RST 0xf70260f4
SC2:BL:fb9e82;ID:00566015C131152A;FEAT:30F:1FFE0000:B002F:1;POC:FF;RCY:0;OVD:0;DFU:0;eMMC:0;RD-2:0;CHK:0;RVK-N:8000;RVK-C:8000;RVK-A:800;RVK-C:8800;RVK-A:800;RVK-C:8800;RVK-N:8000;RVK-C:8800;SCS:0;RVK-N:00004000;RVK-C:0000c800;RVK-N:00002000;RVK-C:0000e800;
build in ddr magic:ddr4
OTP_LIC00 : 0f0300000000fe1f2f000b0000000000
OTP_LIC10 : 00820700aa01fe00ff00001f00400300
OTP_LIC20 : ffffffbf00000000c280000000000001
OTP_LIC30 : 000000f201000000ff0200f207000000
TE: 138316
BL2 Built : 20:42:11, Aug 9 2021. sc2 griscure-review-sc2-bl2-08032020-120-g922477b - jenkins@walle02-sh
Board ID = 1
Set sys clock to 24Mhz
gp1pll is 1200Mhz. Locked
syspll is 1512Mhz. Locked
Set sys clock to 167Mhz
hifipll is 1800Mhz. Locked
bl2_platform_setup
boot area list:
1STBLOB 00000200 00040000
BL2E 00040200 00013000
BL2X 00053200 00011000
DDRFIP 00064200 00040000
DEVFIP 000a4200 00300000
s_setup from rom:00010081
dma mode
DDR driver_vesion: LPDDR4_PHY_V_0_1_23 build time: Aug 9 2021 20:42:05
ddr clk to 672MHz
ddr fw flag:1
fw_type:1, cfg max:3, mask:0007
try next fw type:0
fw_type:0, cfg max:3, mask:0007
DDR3 probe
ddr clk to 672MHz
Load: DDRFIP From: eMMC - 3.2 src: 00000000, dst: f700ab90, size: 00009600sdemmc src: ;
Check phy result
dram_init
read enable training
fine write leveling
Training has failed!
1D training failed
fw_type:0, cfg max:3, mask:0006
DDR3 probe
ddr clk to 672MHz
Check phy result
dram_init
read enable training
fine write leveling
Training has failed!
1D training failed
fw_type:0, cfg max:3, mask:0004
DDR3 probe
ddr clk to 672MHz
Check phy result
dram_init
read enable training
fine write leveling
Training has failed!
1D training failed
fw_type:0, cfg max:3, mask:0000
All ddr config checked...
boot times 0DDR RST
RST 0xf70260f4
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