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发表于 2021-1-19 23:20:39
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#define SET_BIT(R, BIT) (R |= (1 << BIT))
#define CLR_BIT(R, BIT) (R &= ~(1 << BIT))
#define GET_BIT(R, BIT) (((R & (1 << BIT)) >> BIT) & 0x01)
#define EaxSFR() gBIT_TMP = EA; EA = 0; P_SW2 |= 0x80 /* MOVX A,@DPTR/MOVX @DPTR,A指令的操作对象为扩展SFR(XSFR) */
#define EaxRAM() P_SW2 &= ~0x80; EA = gBIT_TMP /* MOVX A,@DPTR/MOVX @DPTR,A指令的操作对象为扩展RAM(XRAM) */
#define set_P_SW2_EAXFR SET_BIT(P_SW2, 7)
#define clr_P_SW2_EAXFR CLR_BIT(P_SW2, 7)
#define get_P_SW2_EAXFR GET_BIT(P_SW2, 7)
#define Set_All_GPIO_Input_Mode P0M1 = 0xff; P0M0 = 0x00; P1M1 = 0xff; P1M0 = 0x00; P2M1 = 0xff; P2M0 = 0x00; P3M1 = 0xff; P3M0 = 0x00; P4M1 = 0xff; P4M0 = 0x00; P5M1 = 0xff; P5M0 = 0x00; P6M1 = 0xff; P6M0 = 0x00; P7M1 = 0xff; P7M0 = 0x00
#define Set_All_GPIO_Quasi_Mode P0M1 = 0x00; P0M0 = 0x00; P1M1 = 0x00; P1M0 = 0x00; P2M1 = 0x00; P2M0 = 0x00; P3M1 = 0x00; P3M0 = 0x00; P4M1 = 0x00; P4M0 = 0x00; P5M1 = 0x00; P5M0 = 0x00; P6M1 = 0x00; P6M0 = 0x00; P7M1 = 0x00; P7M0 = 0x00
//----------------- Define Port as Quasi mode ----------------
#define P00_Quasi_Mode CLR_BIT(P0M1, 0); CLR_BIT(P0M0, 0)
#define P01_Quasi_Mode CLR_BIT(P0M1, 1); CLR_BIT(P0M0, 1)
#define P02_Quasi_Mode CLR_BIT(P0M1, 2); CLR_BIT(P0M0, 2)
#define P03_Quasi_Mode CLR_BIT(P0M1, 3); CLR_BIT(P0M0, 3)
#define P04_Quasi_Mode CLR_BIT(P0M1, 4); CLR_BIT(P0M0, 4)
#define P05_Quasi_Mode CLR_BIT(P0M1, 5); CLR_BIT(P0M0, 5)
#define P06_Quasi_Mode CLR_BIT(P0M1, 6); CLR_BIT(P0M0, 6)
#define P07_Quasi_Mode CLR_BIT(P0M1, 7); CLR_BIT(P0M0, 7)
#define P10_Quasi_Mode CLR_BIT(P1M1, 0); CLR_BIT(P1M0, 0)
#define P11_Quasi_Mode CLR_BIT(P1M1, 1); CLR_BIT(P1M0, 1)
#define P12_Quasi_Mode CLR_BIT(P1M1, 2); CLR_BIT(P1M0, 2)
#define P13_Quasi_Mode CLR_BIT(P1M1, 3); CLR_BIT(P1M0, 3)
#define P14_Quasi_Mode CLR_BIT(P1M1, 4); CLR_BIT(P1M0, 4)
#define P15_Quasi_Mode CLR_BIT(P1M1, 5); CLR_BIT(P1M0, 5)
#define P16_Quasi_Mode CLR_BIT(P1M1, 6); CLR_BIT(P1M0, 6)
#define P17_Quasi_Mode CLR_BIT(P1M1, 7); CLR_BIT(P1M0, 7)
#define P20_Quasi_Mode CLR_BIT(P2M1, 0); CLR_BIT(P2M0, 0)
#define P21_Quasi_Mode CLR_BIT(P2M1, 1); CLR_BIT(P2M0, 1)
#define P22_Quasi_Mode CLR_BIT(P2M1, 2); CLR_BIT(P2M0, 2)
#define P23_Quasi_Mode CLR_BIT(P2M1, 3); CLR_BIT(P2M0, 3)
#define P24_Quasi_Mode CLR_BIT(P2M1, 4); CLR_BIT(P2M0, 4)
#define P25_Quasi_Mode CLR_BIT(P2M1, 5); CLR_BIT(P2M0, 5)
#define P26_Quasi_Mode CLR_BIT(P2M1, 6); CLR_BIT(P2M0, 6)
#define P27_Quasi_Mode CLR_BIT(P2M1, 7); CLR_BIT(P2M0, 7)
#define P30_Quasi_Mode CLR_BIT(P3M1, 0); CLR_BIT(P3M0, 0)
#define P31_Quasi_Mode CLR_BIT(P3M1, 1); CLR_BIT(P3M0, 1)
#define P32_Quasi_Mode CLR_BIT(P3M1, 2); CLR_BIT(P3M0, 2)
#define P33_Quasi_Mode CLR_BIT(P3M1, 3); CLR_BIT(P3M0, 3)
#define P34_Quasi_Mode CLR_BIT(P3M1, 4); CLR_BIT(P3M0, 4)
#define P35_Quasi_Mode CLR_BIT(P3M1, 5); CLR_BIT(P3M0, 5)
#define P36_Quasi_Mode CLR_BIT(P3M1, 6); CLR_BIT(P3M0, 6)
#define P37_Quasi_Mode CLR_BIT(P3M1, 7); CLR_BIT(P3M0, 7)
#define P40_Quasi_Mode CLR_BIT(P4M1, 0); CLR_BIT(P4M0, 0)
#define P41_Quasi_Mode CLR_BIT(P4M1, 1); CLR_BIT(P4M0, 1)
#define P42_Quasi_Mode CLR_BIT(P4M1, 2); CLR_BIT(P4M0, 2)
#define P43_Quasi_Mode CLR_BIT(P4M1, 3); CLR_BIT(P4M0, 3)
#define P44_Quasi_Mode CLR_BIT(P4M1, 4); CLR_BIT(P4M0, 4)
#define P45_Quasi_Mode CLR_BIT(P4M1, 5); CLR_BIT(P4M0, 5)
#define P46_Quasi_Mode CLR_BIT(P4M1, 6); CLR_BIT(P4M0, 6)
#define P47_Quasi_Mode CLR_BIT(P4M1, 7); CLR_BIT(P4M0, 7)
#define P50_Quasi_Mode CLR_BIT(P5M1, 0); CLR_BIT(P5M0, 0)
#define P51_Quasi_Mode CLR_BIT(P5M1, 1); CLR_BIT(P5M0, 1)
#define P52_Quasi_Mode CLR_BIT(P5M1, 2); CLR_BIT(P5M0, 2)
#define P53_Quasi_Mode CLR_BIT(P5M1, 3); CLR_BIT(P5M0, 3)
#define P54_Quasi_Mode CLR_BIT(P5M1, 4); CLR_BIT(P5M0, 4)
#define P60_Quasi_Mode CLR_BIT(P6M1, 0); CLR_BIT(P6M0, 0)
#define P61_Quasi_Mode CLR_BIT(P6M1, 1); CLR_BIT(P6M0, 1)
#define P62_Quasi_Mode CLR_BIT(P6M1, 2); CLR_BIT(P6M0, 2)
#define P63_Quasi_Mode CLR_BIT(P6M1, 3); CLR_BIT(P6M0, 3)
#define P64_Quasi_Mode CLR_BIT(P6M1, 4); CLR_BIT(P6M0, 4)
#define P65_Quasi_Mode CLR_BIT(P6M1, 5); CLR_BIT(P6M0, 5)
#define P66_Quasi_Mode CLR_BIT(P6M1, 6); CLR_BIT(P6M0, 6)
#define P67_Quasi_Mode CLR_BIT(P6M1, 7); CLR_BIT(P6M0, 7)
#define P70_Quasi_Mode CLR_BIT(P7M1, 0); CLR_BIT(P7M0, 0)
#define P71_Quasi_Mode CLR_BIT(P7M1, 1); CLR_BIT(P7M0, 1)
#define P72_Quasi_Mode CLR_BIT(P7M1, 2); CLR_BIT(P7M0, 2)
#define P73_Quasi_Mode CLR_BIT(P7M1, 3); CLR_BIT(P7M0, 3)
#define P74_Quasi_Mode CLR_BIT(P7M1, 4); CLR_BIT(P7M0, 4)
#define P75_Quasi_Mode CLR_BIT(P7M1, 5); CLR_BIT(P7M0, 5)
#define P76_Quasi_Mode CLR_BIT(P7M1, 6); CLR_BIT(P7M0, 6)
#define P77_Quasi_Mode CLR_BIT(P7M1, 7); CLR_BIT(P7M0, 7)
//------------ Define Port as Push Pull mode -----------
#define P00_PushPull_Mode CLR_BIT(P0M1, 0); SET_BIT(P0M0, 0)
#define P01_PushPull_Mode CLR_BIT(P0M1, 1); SET_BIT(P0M0, 1)
#define P02_PushPull_Mode CLR_BIT(P0M1, 2); SET_BIT(P0M0, 2)
#define P03_PushPull_Mode CLR_BIT(P0M1, 3); SET_BIT(P0M0, 3)
#define P04_PushPull_Mode CLR_BIT(P0M1, 4); SET_BIT(P0M0, 4)
#define P05_PushPull_Mode CLR_BIT(P0M1, 5); SET_BIT(P0M0, 5)
#define P06_PushPull_Mode CLR_BIT(P0M1, 6); SET_BIT(P0M0, 6)
#define P07_PushPull_Mode CLR_BIT(P0M1, 7); SET_BIT(P0M0, 7)
#define P10_PushPull_Mode CLR_BIT(P1M1, 0); SET_BIT(P1M0, 0)
#define P11_PushPull_Mode CLR_BIT(P1M1, 1); SET_BIT(P1M0, 1)
#define P12_PushPull_Mode CLR_BIT(P1M1, 2); SET_BIT(P1M0, 2)
#define P13_PushPull_Mode CLR_BIT(P1M1, 3); SET_BIT(P1M0, 3)
#define P14_PushPull_Mode CLR_BIT(P1M1, 4); SET_BIT(P1M0, 4)
#define P15_PushPull_Mode CLR_BIT(P1M1, 5); SET_BIT(P1M0, 5)
#define P16_PushPull_Mode CLR_BIT(P1M1, 6); SET_BIT(P1M0, 6)
#define P17_PushPull_Mode CLR_BIT(P1M1, 7); SET_BIT(P1M0, 7)
#define P20_PushPull_Mode CLR_BIT(P2M1, 0); SET_BIT(P2M0, 0)
#define P21_PushPull_Mode CLR_BIT(P2M1, 1); SET_BIT(P2M0, 1)
#define P22_PushPull_Mode CLR_BIT(P2M1, 2); SET_BIT(P2M0, 2)
#define P23_PushPull_Mode CLR_BIT(P2M1, 3); SET_BIT(P2M0, 3)
#define P24_PushPull_Mode CLR_BIT(P2M1, 4); SET_BIT(P2M0, 4)
#define P25_PushPull_Mode CLR_BIT(P2M1, 5); SET_BIT(P2M0, 5)
#define P26_PushPull_Mode CLR_BIT(P2M1, 6); SET_BIT(P2M0, 6)
#define P27_PushPull_Mode CLR_BIT(P2M1, 7); SET_BIT(P2M0, 7)
#define P30_PushPull_Mode CLR_BIT(P3M1, 0); SET_BIT(P3M0, 0)
#define P31_PushPull_Mode CLR_BIT(P3M1, 1); SET_BIT(P3M0, 1)
#define P32_PushPull_Mode CLR_BIT(P3M1, 2); SET_BIT(P3M0, 2)
#define P33_PushPull_Mode CLR_BIT(P3M1, 3); SET_BIT(P3M0, 3)
#define P34_PushPull_Mode CLR_BIT(P3M1, 4); SET_BIT(P3M0, 4)
#define P35_PushPull_Mode CLR_BIT(P3M1, 5); SET_BIT(P3M0, 5)
#define P36_PushPull_Mode CLR_BIT(P3M1, 6); SET_BIT(P3M0, 6)
#define P37_PushPull_Mode CLR_BIT(P3M1, 7); SET_BIT(P3M0, 7)
#define P40_PushPull_Mode CLR_BIT(P4M1, 0); SET_BIT(P4M0, 0)
#define P41_PushPull_Mode CLR_BIT(P4M1, 1); SET_BIT(P4M0, 1)
#define P42_PushPull_Mode CLR_BIT(P4M1, 2); SET_BIT(P4M0, 2)
#define P43_PushPull_Mode CLR_BIT(P4M1, 3); SET_BIT(P4M0, 3)
#define P44_PushPull_Mode CLR_BIT(P4M1, 4); SET_BIT(P4M0, 4)
#define P45_PushPull_Mode CLR_BIT(P4M1, 5); SET_BIT(P4M0, 5)
#define P46_PushPull_Mode CLR_BIT(P4M1, 6); SET_BIT(P4M0, 6)
#define P47_PushPull_Mode CLR_BIT(P4M1, 7); SET_BIT(P4M0, 7)
#define P50_PushPull_Mode CLR_BIT(P5M1, 0); SET_BIT(P5M0, 0)
#define P51_PushPull_Mode CLR_BIT(P5M1, 1); SET_BIT(P5M0, 1)
#define P52_PushPull_Mode CLR_BIT(P5M1, 2); SET_BIT(P5M0, 2)
#define P53_PushPull_Mode CLR_BIT(P5M1, 3); SET_BIT(P5M0, 3)
#define P54_PushPull_Mode CLR_BIT(P5M1, 4); SET_BIT(P5M0, 4)
#define P60_PushPull_Mode CLR_BIT(P6M1, 0); SET_BIT(P6M0, 0)
#define P61_PushPull_Mode CLR_BIT(P6M1, 1); SET_BIT(P6M0, 1)
#define P62_PushPull_Mode CLR_BIT(P6M1, 2); SET_BIT(P6M0, 2)
#define P63_PushPull_Mode CLR_BIT(P6M1, 3); SET_BIT(P6M0, 3)
#define P64_PushPull_Mode CLR_BIT(P6M1, 4); SET_BIT(P6M0, 4)
#define P65_PushPull_Mode CLR_BIT(P6M1, 5); SET_BIT(P6M0, 5)
#define P66_PushPull_Mode CLR_BIT(P6M1, 6); SET_BIT(P6M0, 6)
#define P67_PushPull_Mode CLR_BIT(P6M1, 7); SET_BIT(P6M0, 7)
#define P70_PushPull_Mode CLR_BIT(P7M1, 0); SET_BIT(P7M0, 0)
#define P71_PushPull_Mode CLR_BIT(P7M1, 1); SET_BIT(P7M0, 1)
#define P72_PushPull_Mode CLR_BIT(P7M1, 2); SET_BIT(P7M0, 2)
#define P73_PushPull_Mode CLR_BIT(P7M1, 3); SET_BIT(P7M0, 3)
#define P74_PushPull_Mode CLR_BIT(P7M1, 4); SET_BIT(P7M0, 4)
#define P75_PushPull_Mode CLR_BIT(P7M1, 5); SET_BIT(P7M0, 5)
#define P76_PushPull_Mode CLR_BIT(P7M1, 6); SET_BIT(P7M0, 6)
#define P77_PushPull_Mode CLR_BIT(P7M1, 7); SET_BIT(P7M0, 7)
//------------- Define Port as Input mode ------------
#define P00_Input_Mode SET_BIT(P0M1, 0); CLR_BIT(P0M0, 0)
#define P01_Input_Mode SET_BIT(P0M1, 1); CLR_BIT(P0M0, 1)
#define P02_Input_Mode SET_BIT(P0M1, 2); CLR_BIT(P0M0, 2)
#define P03_Input_Mode SET_BIT(P0M1, 3); CLR_BIT(P0M0, 3)
#define P04_Input_Mode SET_BIT(P0M1, 4); CLR_BIT(P0M0, 4)
#define P05_Input_Mode SET_BIT(P0M1, 5); CLR_BIT(P0M0, 5)
#define P06_Input_Mode SET_BIT(P0M1, 6); CLR_BIT(P0M0, 6)
#define P07_Input_Mode SET_BIT(P0M1, 7); CLR_BIT(P0M0, 7)
#define P10_Input_Mode SET_BIT(P1M1, 0); CLR_BIT(P1M0, 0)
#define P11_Input_Mode SET_BIT(P1M1, 1); CLR_BIT(P1M0, 1)
#define P12_Input_Mode SET_BIT(P1M1, 2); CLR_BIT(P1M0, 2)
#define P13_Input_Mode SET_BIT(P1M1, 3); CLR_BIT(P1M0, 3)
#define P14_Input_Mode SET_BIT(P1M1, 4); CLR_BIT(P1M0, 4)
#define P15_Input_Mode SET_BIT(P1M1, 5); CLR_BIT(P1M0, 5)
#define P16_Input_Mode SET_BIT(P1M1, 6); CLR_BIT(P1M0, 6)
#define P17_Input_Mode SET_BIT(P1M1, 7); CLR_BIT(P1M0, 7)
#define P20_Input_Mode SET_BIT(P2M1, 0); CLR_BIT(P2M0, 0)
#define P21_Input_Mode SET_BIT(P2M1, 1); CLR_BIT(P2M0, 1)
#define P22_Input_Mode SET_BIT(P2M1, 2); CLR_BIT(P2M0, 2)
#define P23_Input_Mode SET_BIT(P2M1, 3); CLR_BIT(P2M0, 3)
#define P24_Input_Mode SET_BIT(P2M1, 4); CLR_BIT(P2M0, 4)
#define P25_Input_Mode SET_BIT(P2M1, 5); CLR_BIT(P2M0, 5)
#define P26_Input_Mode SET_BIT(P2M1, 6); CLR_BIT(P2M0, 6)
#define P27_Input_Mode SET_BIT(P2M1, 7); CLR_BIT(P2M0, 7)
#define P30_Input_Mode SET_BIT(P3M1, 0); CLR_BIT(P3M0, 0)
#define P31_Input_Mode SET_BIT(P3M1, 1); CLR_BIT(P3M0, 1)
#define P32_Input_Mode SET_BIT(P3M1, 2); CLR_BIT(P3M0, 2)
#define P33_Input_Mode SET_BIT(P3M1, 3); CLR_BIT(P3M0, 3)
#define P34_Input_Mode SET_BIT(P3M1, 4); CLR_BIT(P3M0, 4)
#define P35_Input_Mode SET_BIT(P3M1, 5); CLR_BIT(P3M0, 5)
#define P36_Input_Mode SET_BIT(P3M1, 6); CLR_BIT(P3M0, 6)
#define P37_Input_Mode SET_BIT(P3M1, 7); CLR_BIT(P3M0, 7)
#define P40_Input_Mode SET_BIT(P4M1, 0); CLR_BIT(P4M0, 0)
#define P41_Input_Mode SET_BIT(P4M1, 1); CLR_BIT(P4M0, 1)
#define P42_Input_Mode SET_BIT(P4M1, 2); CLR_BIT(P4M0, 2)
#define P43_Input_Mode SET_BIT(P4M1, 3); CLR_BIT(P4M0, 3)
#define P44_Input_Mode SET_BIT(P4M1, 4); CLR_BIT(P4M0, 4)
#define P45_Input_Mode SET_BIT(P4M1, 5); CLR_BIT(P4M0, 5)
#define P46_Input_Mode SET_BIT(P4M1, 6); CLR_BIT(P4M0, 6)
#define P47_Input_Mode SET_BIT(P4M1, 7); CLR_BIT(P4M0, 7)
#define P50_Input_Mode SET_BIT(P5M1, 0); CLR_BIT(P5M0, 0)
#define P51_Input_Mode SET_BIT(P5M1, 1); CLR_BIT(P5M0, 1)
#define P52_Input_Mode SET_BIT(P5M1, 2); CLR_BIT(P5M0, 2)
#define P53_Input_Mode SET_BIT(P5M1, 3); CLR_BIT(P5M0, 3)
#define P54_Input_Mode SET_BIT(P5M1, 4); CLR_BIT(P5M0, 4)
#define P60_Input_Mode SET_BIT(P6M1, 0); CLR_BIT(P6M0, 0)
#define P61_Input_Mode SET_BIT(P6M1, 1); CLR_BIT(P6M0, 1)
#define P62_Input_Mode SET_BIT(P6M1, 2); CLR_BIT(P6M0, 2)
#define P63_Input_Mode SET_BIT(P6M1, 3); CLR_BIT(P6M0, 3)
#define P64_Input_Mode SET_BIT(P6M1, 4); CLR_BIT(P6M0, 4)
#define P65_Input_Mode SET_BIT(P6M1, 5); CLR_BIT(P6M0, 5)
#define P66_Input_Mode SET_BIT(P6M1, 6); CLR_BIT(P6M0, 6)
#define P67_Input_Mode SET_BIT(P6M1, 7); CLR_BIT(P6M0, 7)
#define P70_Input_Mode SET_BIT(P7M1, 0); CLR_BIT(P7M0, 0)
#define P71_Input_Mode SET_BIT(P7M1, 1); CLR_BIT(P7M0, 1)
#define P72_Input_Mode SET_BIT(P7M1, 2); CLR_BIT(P7M0, 2)
#define P73_Input_Mode SET_BIT(P7M1, 3); CLR_BIT(P7M0, 3)
#define P74_Input_Mode SET_BIT(P7M1, 4); CLR_BIT(P7M0, 4)
#define P75_Input_Mode SET_BIT(P7M1, 5); CLR_BIT(P7M0, 5)
#define P76_Input_Mode SET_BIT(P7M1, 6); CLR_BIT(P7M0, 6)
#define P77_Input_Mode SET_BIT(P7M1, 7); CLR_BIT(P7M0, 7)
//------------- Define Port as OpenDrain mode ------------
#define P00_OpenDrain_Mode SET_BIT(P0M1, 0); SET_BIT(P0M0, 0)
#define P01_OpenDrain_Mode SET_BIT(P0M1, 1); SET_BIT(P0M0, 1)
#define P02_OpenDrain_Mode SET_BIT(P0M1, 2); SET_BIT(P0M0, 2)
#define P03_OpenDrain_Mode SET_BIT(P0M1, 3); SET_BIT(P0M0, 3)
#define P04_OpenDrain_Mode SET_BIT(P0M1, 4); SET_BIT(P0M0, 4)
#define P05_OpenDrain_Mode SET_BIT(P0M1, 5); SET_BIT(P0M0, 5)
#define P06_OpenDrain_Mode SET_BIT(P0M1, 6); SET_BIT(P0M0, 6)
#define P07_OpenDrain_Mode SET_BIT(P0M1, 7); SET_BIT(P0M0, 7)
#define P10_OpenDrain_Mode SET_BIT(P1M1, 0); SET_BIT(P1M0, 0)
#define P11_OpenDrain_Mode SET_BIT(P1M1, 1); SET_BIT(P1M0, 1)
#define P12_OpenDrain_Mode SET_BIT(P1M1, 2); SET_BIT(P1M0, 2)
#define P13_OpenDrain_Mode SET_BIT(P1M1, 3); SET_BIT(P1M0, 3)
#define P14_OpenDrain_Mode SET_BIT(P1M1, 4); SET_BIT(P1M0, 4)
#define P15_OpenDrain_Mode SET_BIT(P1M1, 5); SET_BIT(P1M0, 5)
#define P16_OpenDrain_Mode SET_BIT(P1M1, 6); SET_BIT(P1M0, 6)
#define P17_OpenDrain_Mode SET_BIT(P1M1, 7); SET_BIT(P1M0, 7)
#define P20_OpenDrain_Mode SET_BIT(P2M1, 0); SET_BIT(P2M0, 0)
#define P21_OpenDrain_Mode SET_BIT(P2M1, 1); SET_BIT(P2M0, 1)
#define P22_OpenDrain_Mode SET_BIT(P2M1, 2); SET_BIT(P2M0, 2)
#define P23_OpenDrain_Mode SET_BIT(P2M1, 3); SET_BIT(P2M0, 3)
#define P24_OpenDrain_Mode SET_BIT(P2M1, 4); SET_BIT(P2M0, 4)
#define P25_OpenDrain_Mode SET_BIT(P2M1, 5); SET_BIT(P2M0, 5)
#define P26_OpenDrain_Mode SET_BIT(P2M1, 6); SET_BIT(P2M0, 6)
#define P27_OpenDrain_Mode SET_BIT(P2M1, 7); SET_BIT(P2M0, 7)
#define P30_OpenDrain_Mode SET_BIT(P3M1, 0); SET_BIT(P3M0, 0)
#define P31_OpenDrain_Mode SET_BIT(P3M1, 1); SET_BIT(P3M0, 1)
#define P32_OpenDrain_Mode SET_BIT(P3M1, 2); SET_BIT(P3M0, 2)
#define P33_OpenDrain_Mode SET_BIT(P3M1, 3); SET_BIT(P3M0, 3)
#define P34_OpenDrain_Mode SET_BIT(P3M1, 4); SET_BIT(P3M0, 4)
#define P35_OpenDrain_Mode SET_BIT(P3M1, 5); SET_BIT(P3M0, 5)
#define P36_OpenDrain_Mode SET_BIT(P3M1, 6); SET_BIT(P3M0, 6)
#define P37_OpenDrain_Mode SET_BIT(P3M1, 7); SET_BIT(P3M0, 7)
#define P40_OpenDrain_Mode SET_BIT(P4M1, 0); SET_BIT(P4M0, 0)
#define P41_OpenDrain_Mode SET_BIT(P4M1, 1); SET_BIT(P4M0, 1)
#define P42_OpenDrain_Mode SET_BIT(P4M1, 2); SET_BIT(P4M0, 2)
#define P43_OpenDrain_Mode SET_BIT(P4M1, 3); SET_BIT(P4M0, 3)
#define P44_OpenDrain_Mode SET_BIT(P4M1, 4); SET_BIT(P4M0, 4)
#define P45_OpenDrain_Mode SET_BIT(P4M1, 5); SET_BIT(P4M0, 5)
#define P46_OpenDrain_Mode SET_BIT(P4M1, 6); SET_BIT(P4M0, 6)
#define P47_OpenDrain_Mode SET_BIT(P4M1, 7); SET_BIT(P4M0, 7)
#define P50_OpenDrain_Mode SET_BIT(P5M1, 0); SET_BIT(P5M0, 0)
#define P51_OpenDrain_Mode SET_BIT(P5M1, 1); SET_BIT(P5M0, 1)
#define P52_OpenDrain_Mode SET_BIT(P5M1, 2); SET_BIT(P5M0, 2)
#define P53_OpenDrain_Mode SET_BIT(P5M1, 3); SET_BIT(P5M0, 3)
#define P54_OpenDrain_Mode SET_BIT(P5M1, 4); SET_BIT(P5M0, 4)
#define P60_OpenDrain_Mode SET_BIT(P6M1, 0); SET_BIT(P6M0, 0)
#define P61_OpenDrain_Mode SET_BIT(P6M1, 1); SET_BIT(P6M0, 1)
#define P62_OpenDrain_Mode SET_BIT(P6M1, 2); SET_BIT(P6M0, 2)
#define P63_OpenDrain_Mode SET_BIT(P6M1, 3); SET_BIT(P6M0, 3)
#define P64_OpenDrain_Mode SET_BIT(P6M1, 4); SET_BIT(P6M0, 4)
#define P65_OpenDrain_Mode SET_BIT(P6M1, 5); SET_BIT(P6M0, 5)
#define P66_OpenDrain_Mode SET_BIT(P6M1, 6); SET_BIT(P6M0, 6)
#define P67_OpenDrain_Mode SET_BIT(P6M1, 7); SET_BIT(P6M0, 7)
#define P70_OpenDrain_Mode SET_BIT(P7M1, 0); SET_BIT(P7M0, 0)
#define P71_OpenDrain_Mode SET_BIT(P7M1, 1); SET_BIT(P7M0, 1)
#define P72_OpenDrain_Mode SET_BIT(P7M1, 2); SET_BIT(P7M0, 2)
#define P73_OpenDrain_Mode SET_BIT(P7M1, 3); SET_BIT(P7M0, 3)
#define P74_OpenDrain_Mode SET_BIT(P7M1, 4); SET_BIT(P7M0, 4)
#define P75_OpenDrain_Mode SET_BIT(P7M1, 5); SET_BIT(P7M0, 5)
#define P76_OpenDrain_Mode SET_BIT(P7M1, 6); SET_BIT(P7M0, 6)
#define P77_OpenDrain_Mode SET_BIT(P7M1, 7); SET_BIT(P7M0, 7)
//---------------- Define Port as PullUp mode ----------------
#define P00_Enable_PullUp SET_BIT(P0PU, 0)
#define P01_Enable_PullUp SET_BIT(P0PU, 1)
#define P02_Enable_PullUp SET_BIT(P0PU, 2)
#define P03_Enable_PullUp SET_BIT(P0PU, 3)
#define P04_Enable_PullUp SET_BIT(P0PU, 4)
#define P05_Enable_PullUp SET_BIT(P0PU, 5)
#define P06_Enable_PullUp SET_BIT(P0PU, 6)
#define P07_Enable_PullUp SET_BIT(P0PU, 7)
#define P10_Enable_PullUp SET_BIT(P1PU, 0)
#define P11_Enable_PullUp SET_BIT(P1PU, 1)
#define P12_Enable_PullUp SET_BIT(P1PU, 2)
#define P13_Enable_PullUp SET_BIT(P1PU, 3)
#define P14_Enable_PullUp SET_BIT(P1PU, 4)
#define P15_Enable_PullUp SET_BIT(P1PU, 5)
#define P16_Enable_PullUp SET_BIT(P1PU, 6)
#define P17_Enable_PullUp SET_BIT(P1PU, 7)
#define P20_Enable_PullUp SET_BIT(P2PU, 0)
#define P21_Enable_PullUp SET_BIT(P2PU, 1)
#define P22_Enable_PullUp SET_BIT(P2PU, 2)
#define P23_Enable_PullUp SET_BIT(P2PU, 3)
#define P24_Enable_PullUp SET_BIT(P2PU, 4)
#define P25_Enable_PullUp SET_BIT(P2PU, 5)
#define P26_Enable_PullUp SET_BIT(P2PU, 6)
#define P27_Enable_PullUp SET_BIT(P2PU, 7)
#define P30_Enable_PullUp SET_BIT(P3PU, 0)
#define P31_Enable_PullUp SET_BIT(P3PU, 1)
#define P32_Enable_PullUp SET_BIT(P3PU, 2)
#define P33_Enable_PullUp SET_BIT(P3PU, 3)
#define P34_Enable_PullUp SET_BIT(P3PU, 4)
#define P35_Enable_PullUp SET_BIT(P3PU, 5)
#define P36_Enable_PullUp SET_BIT(P3PU, 6)
#define P37_Enable_PullUp SET_BIT(P3PU, 7)
#define P40_Enable_PullUp SET_BIT(P4PU, 0)
#define P41_Enable_PullUp SET_BIT(P4PU, 1)
#define P42_Enable_PullUp SET_BIT(P4PU, 2)
#define P43_Enable_PullUp SET_BIT(P4PU, 3)
#define P44_Enable_PullUp SET_BIT(P4PU, 4)
#define P45_Enable_PullUp SET_BIT(P4PU, 5)
#define P46_Enable_PullUp SET_BIT(P4PU, 6)
#define P47_Enable_PullUp SET_BIT(P4PU, 7)
#define P50_Enable_PullUp SET_BIT(P5PU, 0)
#define P51_Enable_PullUp SET_BIT(P5PU, 1)
#define P52_Enable_PullUp SET_BIT(P5PU, 2)
#define P53_Enable_PullUp SET_BIT(P5PU, 3)
#define P54_Enable_PullUp SET_BIT(P5PU, 4)
#define P60_Enable_PullUp SET_BIT(P6PU, 0)
#define P61_Enable_PullUp SET_BIT(P6PU, 1)
#define P62_Enable_PullUp SET_BIT(P6PU, 2)
#define P63_Enable_PullUp SET_BIT(P6PU, 3)
#define P64_Enable_PullUp SET_BIT(P6PU, 4)
#define P65_Enable_PullUp SET_BIT(P6PU, 5)
#define P66_Enable_PullUp SET_BIT(P6PU, 6)
#define P67_Enable_PullUp SET_BIT(P6PU, 7)
#define P70_Enable_PullUp SET_BIT(P7PU, 0)
#define P71_Enable_PullUp SET_BIT(P7PU, 1)
#define P72_Enable_PullUp SET_BIT(P7PU, 2)
#define P73_Enable_PullUp SET_BIT(P7PU, 3)
#define P74_Enable_PullUp SET_BIT(P7PU, 4)
#define P75_Enable_PullUp SET_BIT(P7PU, 5)
#define P76_Enable_PullUp SET_BIT(P7PU, 6)
#define P77_Enable_PullUp SET_BIT(P7PU, 7)
#define P00_Disable_PullUp CLR_BIT(P0PU, 0)
#define P01_Disable_PullUp CLR_BIT(P0PU, 1)
#define P02_Disable_PullUp CLR_BIT(P0PU, 2)
#define P03_Disable_PullUp CLR_BIT(P0PU, 3)
#define P04_Disable_PullUp CLR_BIT(P0PU, 4)
#define P05_Disable_PullUp CLR_BIT(P0PU, 5)
#define P06_Disable_PullUp CLR_BIT(P0PU, 6)
#define P07_Disable_PullUp CLR_BIT(P0PU, 7)
#define P10_Disable_PullUp CLR_BIT(P1PU, 0)
#define P11_Disable_PullUp CLR_BIT(P1PU, 1)
#define P12_Disable_PullUp CLR_BIT(P1PU, 2)
#define P13_Disable_PullUp CLR_BIT(P1PU, 3)
#define P14_Disable_PullUp CLR_BIT(P1PU, 4)
#define P15_Disable_PullUp CLR_BIT(P1PU, 5)
#define P16_Disable_PullUp CLR_BIT(P1PU, 6)
#define P17_Disable_PullUp CLR_BIT(P1PU, 7)
#define P20_Disable_PullUp CLR_BIT(P2PU, 0)
#define P21_Disable_PullUp CLR_BIT(P2PU, 1)
#define P22_Disable_PullUp CLR_BIT(P2PU, 2)
#define P23_Disable_PullUp CLR_BIT(P2PU, 3)
#define P24_Disable_PullUp CLR_BIT(P2PU, 4)
#define P25_Disable_PullUp CLR_BIT(P2PU, 5)
#define P26_Disable_PullUp CLR_BIT(P2PU, 6)
#define P27_Disable_PullUp CLR_BIT(P2PU, 7)
#define P30_Disable_PullUp CLR_BIT(P3PU, 0)
#define P31_Disable_PullUp CLR_BIT(P3PU, 1)
#define P32_Disable_PullUp CLR_BIT(P3PU, 2)
#define P33_Disable_PullUp CLR_BIT(P3PU, 3)
#define P34_Disable_PullUp CLR_BIT(P3PU, 4)
#define P35_Disable_PullUp CLR_BIT(P3PU, 5)
#define P36_Disable_PullUp CLR_BIT(P3PU, 6)
#define P37_Disable_PullUp CLR_BIT(P3PU, 7)
#define P40_Disable_PullUp CLR_BIT(P4PU, 0)
#define P41_Disable_PullUp CLR_BIT(P4PU, 1)
#define P42_Disable_PullUp CLR_BIT(P4PU, 2)
#define P43_Disable_PullUp CLR_BIT(P4PU, 3)
#define P44_Disable_PullUp CLR_BIT(P4PU, 4)
#define P45_Disable_PullUp CLR_BIT(P4PU, 5)
#define P46_Disable_PullUp CLR_BIT(P4PU, 6)
#define P47_Disable_PullUp CLR_BIT(P4PU, 7)
#define P50_Disable_PullUp CLR_BIT(P5PU, 0)
#define P51_Disable_PullUp CLR_BIT(P5PU, 1)
#define P52_Disable_PullUp CLR_BIT(P5PU, 2)
#define P53_Disable_PullUp CLR_BIT(P5PU, 3)
#define P54_Disable_PullUp CLR_BIT(P5PU, 4)
#define P60_Disable_PullUp CLR_BIT(P6PU, 0)
#define P61_Disable_PullUp CLR_BIT(P6PU, 1)
#define P62_Disable_PullUp CLR_BIT(P6PU, 2)
#define P63_Disable_PullUp CLR_BIT(P6PU, 3)
#define P64_Disable_PullUp CLR_BIT(P6PU, 4)
#define P65_Disable_PullUp CLR_BIT(P6PU, 5)
#define P66_Disable_PullUp CLR_BIT(P6PU, 6)
#define P67_Disable_PullUp CLR_BIT(P6PU, 7)
#define P70_Disable_PullUp CLR_BIT(P7PU, 0)
#define P71_Disable_PullUp CLR_BIT(P7PU, 1)
#define P72_Disable_PullUp CLR_BIT(P7PU, 2)
#define P73_Disable_PullUp CLR_BIT(P7PU, 3)
#define P74_Disable_PullUp CLR_BIT(P7PU, 4)
#define P75_Disable_PullUp CLR_BIT(P7PU, 5)
#define P76_Disable_PullUp CLR_BIT(P7PU, 6)
#define P77_Disable_PullUp CLR_BIT(P7PU, 7)
//----------------- Define Port as NCS mode -----------------
#define P00_Enable_NCS CLR_BIT(P0NCS, 0)
#define P01_Enable_NCS CLR_BIT(P0NCS, 1)
#define P02_Enable_NCS CLR_BIT(P0NCS, 2)
#define P03_Enable_NCS CLR_BIT(P0NCS, 3)
#define P04_Enable_NCS CLR_BIT(P0NCS, 4)
#define P05_Enable_NCS CLR_BIT(P0NCS, 5)
#define P06_Enable_NCS CLR_BIT(P0NCS, 6)
#define P07_Enable_NCS CLR_BIT(P0NCS, 7)
#define P10_Enable_NCS CLR_BIT(P1NCS, 0)
#define P11_Enable_NCS CLR_BIT(P1NCS, 1)
#define P12_Enable_NCS CLR_BIT(P1NCS, 2)
#define P13_Enable_NCS CLR_BIT(P1NCS, 3)
#define P14_Enable_NCS CLR_BIT(P1NCS, 4)
#define P15_Enable_NCS CLR_BIT(P1NCS, 5)
#define P16_Enable_NCS CLR_BIT(P1NCS, 6)
#define P17_Enable_NCS CLR_BIT(P1NCS, 7)
#define P20_Enable_NCS CLR_BIT(P2NCS, 0)
#define P21_Enable_NCS CLR_BIT(P2NCS, 1)
#define P22_Enable_NCS CLR_BIT(P2NCS, 2)
#define P23_Enable_NCS CLR_BIT(P2NCS, 3)
#define P24_Enable_NCS CLR_BIT(P2NCS, 4)
#define P25_Enable_NCS CLR_BIT(P2NCS, 5)
#define P26_Enable_NCS CLR_BIT(P2NCS, 6)
#define P27_Enable_NCS CLR_BIT(P2NCS, 7)
#define P30_Enable_NCS CLR_BIT(P3NCS, 0)
#define P31_Enable_NCS CLR_BIT(P3NCS, 1)
#define P32_Enable_NCS CLR_BIT(P3NCS, 2)
#define P33_Enable_NCS CLR_BIT(P3NCS, 3)
#define P34_Enable_NCS CLR_BIT(P3NCS, 4)
#define P35_Enable_NCS CLR_BIT(P3NCS, 5)
#define P36_Enable_NCS CLR_BIT(P3NCS, 6)
#define P37_Enable_NCS CLR_BIT(P3NCS, 7)
#define P40_Enable_NCS CLR_BIT(P4NCS, 0)
#define P41_Enable_NCS CLR_BIT(P4NCS, 1)
#define P42_Enable_NCS CLR_BIT(P4NCS, 2)
#define P43_Enable_NCS CLR_BIT(P4NCS, 3)
#define P44_Enable_NCS CLR_BIT(P4NCS, 4)
#define P45_Enable_NCS CLR_BIT(P4NCS, 5)
#define P46_Enable_NCS CLR_BIT(P4NCS, 6)
#define P47_Enable_NCS CLR_BIT(P4NCS, 7)
#define P50_Enable_NCS CLR_BIT(P5NCS, 0)
#define P51_Enable_NCS CLR_BIT(P5NCS, 1)
#define P52_Enable_NCS CLR_BIT(P5NCS, 2)
#define P53_Enable_NCS CLR_BIT(P5NCS, 3)
#define P54_Enable_NCS CLR_BIT(P5NCS, 4)
#define P60_Enable_NCS CLR_BIT(P6NCS, 0)
#define P61_Enable_NCS CLR_BIT(P6NCS, 1)
#define P62_Enable_NCS CLR_BIT(P6NCS, 2)
#define P63_Enable_NCS CLR_BIT(P6NCS, 3)
#define P64_Enable_NCS CLR_BIT(P6NCS, 4)
#define P65_Enable_NCS CLR_BIT(P6NCS, 5)
#define P66_Enable_NCS CLR_BIT(P6NCS, 6)
#define P67_Enable_NCS CLR_BIT(P6NCS, 7)
#define P70_Enable_NCS CLR_BIT(P7NCS, 0)
#define P71_Enable_NCS CLR_BIT(P7NCS, 1)
#define P72_Enable_NCS CLR_BIT(P7NCS, 2)
#define P73_Enable_NCS CLR_BIT(P7NCS, 3)
#define P74_Enable_NCS CLR_BIT(P7NCS, 4)
#define P75_Enable_NCS CLR_BIT(P7NCS, 5)
#define P76_Enable_NCS CLR_BIT(P7NCS, 6)
#define P77_Enable_NCS CLR_BIT(P7NCS, 7)
#define P00_Disable_NCS SET_BIT(P0NCS, 0)
#define P01_Disable_NCS SET_BIT(P0NCS, 1)
#define P02_Disable_NCS SET_BIT(P0NCS, 2)
#define P03_Disable_NCS SET_BIT(P0NCS, 3)
#define P04_Disable_NCS SET_BIT(P0NCS, 4)
#define P05_Disable_NCS SET_BIT(P0NCS, 5)
#define P06_Disable_NCS SET_BIT(P0NCS, 6)
#define P07_Disable_NCS SET_BIT(P0NCS, 7)
#define P10_Disable_NCS SET_BIT(P1NCS, 0)
#define P11_Disable_NCS SET_BIT(P1NCS, 1)
#define P12_Disable_NCS SET_BIT(P1NCS, 2)
#define P13_Disable_NCS SET_BIT(P1NCS, 3)
#define P14_Disable_NCS SET_BIT(P1NCS, 4)
#define P15_Disable_NCS SET_BIT(P1NCS, 5)
#define P16_Disable_NCS SET_BIT(P1NCS, 6)
#define P17_Disable_NCS SET_BIT(P1NCS, 7)
#define P20_Disable_NCS SET_BIT(P2NCS, 0)
#define P21_Disable_NCS SET_BIT(P2NCS, 1)
#define P22_Disable_NCS SET_BIT(P2NCS, 2)
#define P23_Disable_NCS SET_BIT(P2NCS, 3)
#define P24_Disable_NCS SET_BIT(P2NCS, 4)
#define P25_Disable_NCS SET_BIT(P2NCS, 5)
#define P26_Disable_NCS SET_BIT(P2NCS, 6)
#define P27_Disable_NCS SET_BIT(P2NCS, 7)
#define P30_Disable_NCS SET_BIT(P3NCS, 0)
#define P31_Disable_NCS SET_BIT(P3NCS, 1)
#define P32_Disable_NCS SET_BIT(P3NCS, 2)
#define P33_Disable_NCS SET_BIT(P3NCS, 3)
#define P34_Disable_NCS SET_BIT(P3NCS, 4)
#define P35_Disable_NCS SET_BIT(P3NCS, 5)
#define P36_Disable_NCS SET_BIT(P3NCS, 6)
#define P37_Disable_NCS SET_BIT(P3NCS, 7)
#define P40_Disable_NCS SET_BIT(P4NCS, 0)
#define P41_Disable_NCS SET_BIT(P4NCS, 1)
#define P42_Disable_NCS SET_BIT(P4NCS, 2)
#define P43_Disable_NCS SET_BIT(P4NCS, 3)
#define P44_Disable_NCS SET_BIT(P4NCS, 4)
#define P45_Disable_NCS SET_BIT(P4NCS, 5)
#define P46_Disable_NCS SET_BIT(P4NCS, 6)
#define P47_Disable_NCS SET_BIT(P4NCS, 7)
#define P50_Disable_NCS SET_BIT(P5NCS, 0)
#define P51_Disable_NCS SET_BIT(P5NCS, 1)
#define P52_Disable_NCS SET_BIT(P5NCS, 2)
#define P53_Disable_NCS SET_BIT(P5NCS, 3)
#define P54_Disable_NCS SET_BIT(P5NCS, 4)
#define P60_Disable_NCS SET_BIT(P6NCS, 0)
#define P61_Disable_NCS SET_BIT(P6NCS, 1)
#define P62_Disable_NCS SET_BIT(P6NCS, 2)
#define P63_Disable_NCS SET_BIT(P6NCS, 3)
#define P64_Disable_NCS SET_BIT(P6NCS, 4)
#define P65_Disable_NCS SET_BIT(P6NCS, 5)
#define P66_Disable_NCS SET_BIT(P6NCS, 6)
#define P67_Disable_NCS SET_BIT(P6NCS, 7)
#define P70_Disable_NCS SET_BIT(P7NCS, 0)
#define P71_Disable_NCS SET_BIT(P7NCS, 1)
#define P72_Disable_NCS SET_BIT(P7NCS, 2)
#define P73_Disable_NCS SET_BIT(P7NCS, 3)
#define P74_Disable_NCS SET_BIT(P7NCS, 4)
#define P75_Disable_NCS SET_BIT(P7NCS, 5)
#define P76_Disable_NCS SET_BIT(P7NCS, 6)
#define P77_Disable_NCS SET_BIT(P7NCS, 7)
//---------------- Define Port as HighSpeed mode -----------------
#define P00_Enable_HighSpeed CLR_BIT(P0SR, 0)
#define P01_Enable_HighSpeed CLR_BIT(P0SR, 1)
#define P02_Enable_HighSpeed CLR_BIT(P0SR, 2)
#define P03_Enable_HighSpeed CLR_BIT(P0SR, 3)
#define P04_Enable_HighSpeed CLR_BIT(P0SR, 4)
#define P05_Enable_HighSpeed CLR_BIT(P0SR, 5)
#define P06_Enable_HighSpeed CLR_BIT(P0SR, 6)
#define P07_Enable_HighSpeed CLR_BIT(P0SR, 7)
#define P10_Enable_HighSpeed CLR_BIT(P1SR, 0)
#define P11_Enable_HighSpeed CLR_BIT(P1SR, 1)
#define P12_Enable_HighSpeed CLR_BIT(P1SR, 2)
#define P13_Enable_HighSpeed CLR_BIT(P1SR, 3)
#define P14_Enable_HighSpeed CLR_BIT(P1SR, 4)
#define P15_Enable_HighSpeed CLR_BIT(P1SR, 5)
#define P16_Enable_HighSpeed CLR_BIT(P1SR, 6)
#define P17_Enable_HighSpeed CLR_BIT(P1SR, 7)
#define P20_Enable_HighSpeed CLR_BIT(P2SR, 0)
#define P21_Enable_HighSpeed CLR_BIT(P2SR, 1)
#define P22_Enable_HighSpeed CLR_BIT(P2SR, 2)
#define P23_Enable_HighSpeed CLR_BIT(P2SR, 3)
#define P24_Enable_HighSpeed CLR_BIT(P2SR, 4)
#define P25_Enable_HighSpeed CLR_BIT(P2SR, 5)
#define P26_Enable_HighSpeed CLR_BIT(P2SR, 6)
#define P27_Enable_HighSpeed CLR_BIT(P2SR, 7)
#define P30_Enable_HighSpeed CLR_BIT(P3SR, 0)
#define P31_Enable_HighSpeed CLR_BIT(P3SR, 1)
#define P32_Enable_HighSpeed CLR_BIT(P3SR, 2)
#define P33_Enable_HighSpeed CLR_BIT(P3SR, 3)
#define P34_Enable_HighSpeed CLR_BIT(P3SR, 4)
#define P35_Enable_HighSpeed CLR_BIT(P3SR, 5)
#define P36_Enable_HighSpeed CLR_BIT(P3SR, 6)
#define P37_Enable_HighSpeed CLR_BIT(P3SR, 7)
#define P40_Enable_HighSpeed CLR_BIT(P4SR, 0)
#define P41_Enable_HighSpeed CLR_BIT(P4SR, 1)
#define P42_Enable_HighSpeed CLR_BIT(P4SR, 2)
#define P43_Enable_HighSpeed CLR_BIT(P4SR, 3)
#define P44_Enable_HighSpeed CLR_BIT(P4SR, 4)
#define P45_Enable_HighSpeed CLR_BIT(P4SR, 5)
#define P46_Enable_HighSpeed CLR_BIT(P4SR, 6)
#define P47_Enable_HighSpeed CLR_BIT(P4SR, 7)
#define P50_Enable_HighSpeed CLR_BIT(P5SR, 0)
#define P51_Enable_HighSpeed CLR_BIT(P5SR, 1)
#define P52_Enable_HighSpeed CLR_BIT(P5SR, 2)
#define P53_Enable_HighSpeed CLR_BIT(P5SR, 3)
#define P54_Enable_HighSpeed CLR_BIT(P5SR, 4)
#define P60_Enable_HighSpeed CLR_BIT(P6SR, 0)
#define P61_Enable_HighSpeed CLR_BIT(P6SR, 1)
#define P62_Enable_HighSpeed CLR_BIT(P6SR, 2)
#define P63_Enable_HighSpeed CLR_BIT(P6SR, 3)
#define P64_Enable_HighSpeed CLR_BIT(P6SR, 4)
#define P65_Enable_HighSpeed CLR_BIT(P6SR, 5)
#define P66_Enable_HighSpeed CLR_BIT(P6SR, 6)
#define P67_Enable_HighSpeed CLR_BIT(P6SR, 7)
#define P70_Enable_HighSpeed CLR_BIT(P7SR, 0)
#define P71_Enable_HighSpeed CLR_BIT(P7SR, 1)
#define P72_Enable_HighSpeed CLR_BIT(P7SR, 2)
#define P73_Enable_HighSpeed CLR_BIT(P7SR, 3)
#define P74_Enable_HighSpeed CLR_BIT(P7SR, 4)
#define P75_Enable_HighSpeed CLR_BIT(P7SR, 5)
#define P76_Enable_HighSpeed CLR_BIT(P7SR, 6)
#define P77_Enable_HighSpeed CLR_BIT(P7SR, 7)
#define P00_Disable_HighSpeed SET_BIT(P0SR, 0)
#define P01_Disable_HighSpeed SET_BIT(P0SR, 1)
#define P02_Disable_HighSpeed SET_BIT(P0SR, 2)
#define P03_Disable_HighSpeed SET_BIT(P0SR, 3)
#define P04_Disable_HighSpeed SET_BIT(P0SR, 4)
#define P05_Disable_HighSpeed SET_BIT(P0SR, 5)
#define P06_Disable_HighSpeed SET_BIT(P0SR, 6)
#define P07_Disable_HighSpeed SET_BIT(P0SR, 7)
#define P10_Disable_HighSpeed SET_BIT(P1SR, 0)
#define P11_Disable_HighSpeed SET_BIT(P1SR, 1)
#define P12_Disable_HighSpeed SET_BIT(P1SR, 2)
#define P13_Disable_HighSpeed SET_BIT(P1SR, 3)
#define P14_Disable_HighSpeed SET_BIT(P1SR, 4)
#define P15_Disable_HighSpeed SET_BIT(P1SR, 5)
#define P16_Disable_HighSpeed SET_BIT(P1SR, 6)
#define P17_Disable_HighSpeed SET_BIT(P1SR, 7)
#define P20_Disable_HighSpeed SET_BIT(P2SR, 0)
#define P21_Disable_HighSpeed SET_BIT(P2SR, 1)
#define P22_Disable_HighSpeed SET_BIT(P2SR, 2)
#define P23_Disable_HighSpeed SET_BIT(P2SR, 3)
#define P24_Disable_HighSpeed SET_BIT(P2SR, 4)
#define P25_Disable_HighSpeed SET_BIT(P2SR, 5)
#define P26_Disable_HighSpeed SET_BIT(P2SR, 6)
#define P27_Disable_HighSpeed SET_BIT(P2SR, 7)
#define P30_Disable_HighSpeed SET_BIT(P3SR, 0)
#define P31_Disable_HighSpeed SET_BIT(P3SR, 1)
#define P32_Disable_HighSpeed SET_BIT(P3SR, 2)
#define P33_Disable_HighSpeed SET_BIT(P3SR, 3)
#define P34_Disable_HighSpeed SET_BIT(P3SR, 4)
#define P35_Disable_HighSpeed SET_BIT(P3SR, 5)
#define P36_Disable_HighSpeed SET_BIT(P3SR, 6)
#define P37_Disable_HighSpeed SET_BIT(P3SR, 7)
#define P40_Disable_HighSpeed SET_BIT(P4SR, 0)
#define P41_Disable_HighSpeed SET_BIT(P4SR, 1)
#define P42_Disable_HighSpeed SET_BIT(P4SR, 2)
#define P43_Disable_HighSpeed SET_BIT(P4SR, 3)
#define P44_Disable_HighSpeed SET_BIT(P4SR, 4)
#define P45_Disable_HighSpeed SET_BIT(P4SR, 5)
#define P46_Disable_HighSpeed SET_BIT(P4SR, 6)
#define P47_Disable_HighSpeed SET_BIT(P4SR, 7)
#define P50_Disable_HighSpeed SET_BIT(P5SR, 0)
#define P51_Disable_HighSpeed SET_BIT(P5SR, 1)
#define P52_Disable_HighSpeed SET_BIT(P5SR, 2)
#define P53_Disable_HighSpeed SET_BIT(P5SR, 3)
#define P54_Disable_HighSpeed SET_BIT(P5SR, 4)
#define P60_Disable_HighSpeed SET_BIT(P6SR, 0)
#define P61_Disable_HighSpeed SET_BIT(P6SR, 1)
#define P62_Disable_HighSpeed SET_BIT(P6SR, 2)
#define P63_Disable_HighSpeed SET_BIT(P6SR, 3)
#define P64_Disable_HighSpeed SET_BIT(P6SR, 4)
#define P65_Disable_HighSpeed SET_BIT(P6SR, 5)
#define P66_Disable_HighSpeed SET_BIT(P6SR, 6)
#define P67_Disable_HighSpeed SET_BIT(P6SR, 7)
#define P70_Disable_HighSpeed SET_BIT(P7SR, 0)
#define P71_Disable_HighSpeed SET_BIT(P7SR, 1)
#define P72_Disable_HighSpeed SET_BIT(P7SR, 2)
#define P73_Disable_HighSpeed SET_BIT(P7SR, 3)
#define P74_Disable_HighSpeed SET_BIT(P7SR, 4)
#define P75_Disable_HighSpeed SET_BIT(P7SR, 5)
#define P76_Disable_HighSpeed SET_BIT(P7SR, 6)
#define P77_Disable_HighSpeed SET_BIT(P7SR, 7)
//----------------- Define Port as HighDrive mode ----------------
#define P00_Enable_HighDrive CLR_BIT(P0DR, 0)
#define P01_Enable_HighDrive CLR_BIT(P0DR, 1)
#define P02_Enable_HighDrive CLR_BIT(P0DR, 2)
#define P03_Enable_HighDrive CLR_BIT(P0DR, 3)
#define P04_Enable_HighDrive CLR_BIT(P0DR, 4)
#define P05_Enable_HighDrive CLR_BIT(P0DR, 5)
#define P06_Enable_HighDrive CLR_BIT(P0DR, 6)
#define P07_Enable_HighDrive CLR_BIT(P0DR, 7)
#define P10_Enable_HighDrive CLR_BIT(P1DR, 0)
#define P11_Enable_HighDrive CLR_BIT(P1DR, 1)
#define P12_Enable_HighDrive CLR_BIT(P1DR, 2)
#define P13_Enable_HighDrive CLR_BIT(P1DR, 3)
#define P14_Enable_HighDrive CLR_BIT(P1DR, 4)
#define P15_Enable_HighDrive CLR_BIT(P1DR, 5)
#define P16_Enable_HighDrive CLR_BIT(P1DR, 6)
#define P17_Enable_HighDrive CLR_BIT(P1DR, 7)
#define P20_Enable_HighDrive CLR_BIT(P2DR, 0)
#define P21_Enable_HighDrive CLR_BIT(P2DR, 1)
#define P22_Enable_HighDrive CLR_BIT(P2DR, 2)
#define P23_Enable_HighDrive CLR_BIT(P2DR, 3)
#define P24_Enable_HighDrive CLR_BIT(P2DR, 4)
#define P25_Enable_HighDrive CLR_BIT(P2DR, 5)
#define P26_Enable_HighDrive CLR_BIT(P2DR, 6)
#define P27_Enable_HighDrive CLR_BIT(P2DR, 7)
#define P30_Enable_HighDrive CLR_BIT(P3DR, 0)
#define P31_Enable_HighDrive CLR_BIT(P3DR, 1)
#define P32_Enable_HighDrive CLR_BIT(P3DR, 2)
#define P33_Enable_HighDrive CLR_BIT(P3DR, 3)
#define P34_Enable_HighDrive CLR_BIT(P3DR, 4)
#define P35_Enable_HighDrive CLR_BIT(P3DR, 5)
#define P36_Enable_HighDrive CLR_BIT(P3DR, 6)
#define P37_Enable_HighDrive CLR_BIT(P3DR, 7)
#define P40_Enable_HighDrive CLR_BIT(P4DR, 0)
#define P41_Enable_HighDrive CLR_BIT(P4DR, 1)
#define P42_Enable_HighDrive CLR_BIT(P4DR, 2)
#define P43_Enable_HighDrive CLR_BIT(P4DR, 3)
#define P44_Enable_HighDrive CLR_BIT(P4DR, 4)
#define P45_Enable_HighDrive CLR_BIT(P4DR, 5)
#define P46_Enable_HighDrive CLR_BIT(P4DR, 6)
#define P47_Enable_HighDrive CLR_BIT(P4DR, 7)
#define P50_Enable_HighDrive CLR_BIT(P5DR, 0)
#define P51_Enable_HighDrive CLR_BIT(P5DR, 1)
#define P52_Enable_HighDrive CLR_BIT(P5DR, 2)
#define P53_Enable_HighDrive CLR_BIT(P5DR, 3)
#define P54_Enable_HighDrive CLR_BIT(P5DR, 4)
#define P60_Enable_HighDrive CLR_BIT(P6DR, 0)
#define P61_Enable_HighDrive CLR_BIT(P6DR, 1)
#define P62_Enable_HighDrive CLR_BIT(P6DR, 2)
#define P63_Enable_HighDrive CLR_BIT(P6DR, 3)
#define P64_Enable_HighDrive CLR_BIT(P6DR, 4)
#define P65_Enable_HighDrive CLR_BIT(P6DR, 5)
#define P66_Enable_HighDrive CLR_BIT(P6DR, 6)
#define P67_Enable_HighDrive CLR_BIT(P6DR, 7)
#define P70_Enable_HighDrive CLR_BIT(P7DR, 0)
#define P71_Enable_HighDrive CLR_BIT(P7DR, 1)
#define P72_Enable_HighDrive CLR_BIT(P7DR, 2)
#define P73_Enable_HighDrive CLR_BIT(P7DR, 3)
#define P74_Enable_HighDrive CLR_BIT(P7DR, 4)
#define P75_Enable_HighDrive CLR_BIT(P7DR, 5)
#define P76_Enable_HighDrive CLR_BIT(P7DR, 6)
#define P77_Enable_HighDrive CLR_BIT(P7DR, 7)
#define P00_Disable_HighDrive SET_BIT(P0DR, 0)
#define P01_Disable_HighDrive SET_BIT(P0DR, 1)
#define P02_Disable_HighDrive SET_BIT(P0DR, 2)
#define P03_Disable_HighDrive SET_BIT(P0DR, 3)
#define P04_Disable_HighDrive SET_BIT(P0DR, 4)
#define P05_Disable_HighDrive SET_BIT(P0DR, 5)
#define P06_Disable_HighDrive SET_BIT(P0DR, 6)
#define P07_Disable_HighDrive SET_BIT(P0DR, 7)
#define P10_Disable_HighDrive SET_BIT(P1DR, 0)
#define P11_Disable_HighDrive SET_BIT(P1DR, 1)
#define P12_Disable_HighDrive SET_BIT(P1DR, 2)
#define P13_Disable_HighDrive SET_BIT(P1DR, 3)
#define P14_Disable_HighDrive SET_BIT(P1DR, 4)
#define P15_Disable_HighDrive SET_BIT(P1DR, 5)
#define P16_Disable_HighDrive SET_BIT(P1DR, 6)
#define P17_Disable_HighDrive SET_BIT(P1DR, 7)
#define P20_Disable_HighDrive SET_BIT(P2DR, 0)
#define P21_Disable_HighDrive SET_BIT(P2DR, 1)
#define P22_Disable_HighDrive SET_BIT(P2DR, 2)
#define P23_Disable_HighDrive SET_BIT(P2DR, 3)
#define P24_Disable_HighDrive SET_BIT(P2DR, 4)
#define P25_Disable_HighDrive SET_BIT(P2DR, 5)
#define P26_Disable_HighDrive SET_BIT(P2DR, 6)
#define P27_Disable_HighDrive SET_BIT(P2DR, 7)
#define P30_Disable_HighDrive SET_BIT(P3DR, 0)
#define P31_Disable_HighDrive SET_BIT(P3DR, 1)
#define P32_Disable_HighDrive SET_BIT(P3DR, 2)
#define P33_Disable_HighDrive SET_BIT(P3DR, 3)
#define P34_Disable_HighDrive SET_BIT(P3DR, 4)
#define P35_Disable_HighDrive SET_BIT(P3DR, 5)
#define P36_Disable_HighDrive SET_BIT(P3DR, 6)
#define P37_Disable_HighDrive SET_BIT(P3DR, 7)
#define P40_Disable_HighDrive SET_BIT(P4DR, 0)
#define P41_Disable_HighDrive SET_BIT(P4DR, 1)
#define P42_Disable_HighDrive SET_BIT(P4DR, 2)
#define P43_Disable_HighDrive SET_BIT(P4DR, 3)
#define P44_Disable_HighDrive SET_BIT(P4DR, 4)
#define P45_Disable_HighDrive SET_BIT(P4DR, 5)
#define P46_Disable_HighDrive SET_BIT(P4DR, 6)
#define P47_Disable_HighDrive SET_BIT(P4DR, 7)
#define P50_Disable_HighDrive SET_BIT(P5DR, 0)
#define P51_Disable_HighDrive SET_BIT(P5DR, 1)
#define P52_Disable_HighDrive SET_BIT(P5DR, 2)
#define P53_Disable_HighDrive SET_BIT(P5DR, 3)
#define P54_Disable_HighDrive SET_BIT(P5DR, 4)
#define P60_Disable_HighDrive SET_BIT(P6DR, 0)
#define P61_Disable_HighDrive SET_BIT(P6DR, 1)
#define P62_Disable_HighDrive SET_BIT(P6DR, 2)
#define P63_Disable_HighDrive SET_BIT(P6DR, 3)
#define P64_Disable_HighDrive SET_BIT(P6DR, 4)
#define P65_Disable_HighDrive SET_BIT(P6DR, 5)
#define P66_Disable_HighDrive SET_BIT(P6DR, 6)
#define P67_Disable_HighDrive SET_BIT(P6DR, 7)
#define P70_Disable_HighDrive SET_BIT(P7DR, 0)
#define P71_Disable_HighDrive SET_BIT(P7DR, 1)
#define P72_Disable_HighDrive SET_BIT(P7DR, 2)
#define P73_Disable_HighDrive SET_BIT(P7DR, 3)
#define P74_Disable_HighDrive SET_BIT(P7DR, 4)
#define P75_Disable_HighDrive SET_BIT(P7DR, 5)
#define P76_Disable_HighDrive SET_BIT(P7DR, 6)
#define P77_Disable_HighDrive SET_BIT(P7DR, 7)
//---------------- Define Port as DigitalInput mode --------------
#define P00_Enable_DigitalInput SET_BIT(P0IE, 0)
#define P01_Enable_DigitalInput SET_BIT(P0IE, 1)
#define P02_Enable_DigitalInput SET_BIT(P0IE, 2)
#define P03_Enable_DigitalInput SET_BIT(P0IE, 3)
#define P04_Enable_DigitalInput SET_BIT(P0IE, 4)
#define P05_Enable_DigitalInput SET_BIT(P0IE, 5)
#define P06_Enable_DigitalInput SET_BIT(P0IE, 6)
#define P07_Enable_DigitalInput SET_BIT(P0IE, 7)
#define P10_Enable_DigitalInput SET_BIT(P1IE, 0)
#define P11_Enable_DigitalInput SET_BIT(P1IE, 1)
#define P12_Enable_DigitalInput SET_BIT(P1IE, 2)
#define P13_Enable_DigitalInput SET_BIT(P1IE, 3)
#define P14_Enable_DigitalInput SET_BIT(P1IE, 4)
#define P15_Enable_DigitalInput SET_BIT(P1IE, 5)
#define P16_Enable_DigitalInput SET_BIT(P1IE, 6)
#define P17_Enable_DigitalInput SET_BIT(P1IE, 7)
#define P30_Enable_DigitalInput SET_BIT(P3IE, 0)
#define P31_Enable_DigitalInput SET_BIT(P3IE, 1)
#define P32_Enable_DigitalInput SET_BIT(P3IE, 2)
#define P33_Enable_DigitalInput SET_BIT(P3IE, 3)
#define P34_Enable_DigitalInput SET_BIT(P3IE, 4)
#define P35_Enable_DigitalInput SET_BIT(P3IE, 5)
#define P36_Enable_DigitalInput SET_BIT(P3IE, 6)
#define P37_Enable_DigitalInput SET_BIT(P3IE, 7)
#define P00_Disable_DigitalInput CLR_BIT(P0IE, 0)
#define P01_Disable_DigitalInput CLR_BIT(P0IE, 1)
#define P02_Disable_DigitalInput CLR_BIT(P0IE, 2)
#define P03_Disable_DigitalInput CLR_BIT(P0IE, 3)
#define P04_Disable_DigitalInput CLR_BIT(P0IE, 4)
#define P05_Disable_DigitalInput CLR_BIT(P0IE, 5)
#define P06_Disable_DigitalInput CLR_BIT(P0IE, 6)
#define P07_Disable_DigitalInput CLR_BIT(P0IE, 7)
#define P10_Disable_DigitalInput CLR_BIT(P1IE, 0)
#define P11_Disable_DigitalInput CLR_BIT(P1IE, 1)
#define P12_Disable_DigitalInput CLR_BIT(P1IE, 2)
#define P13_Disable_DigitalInput CLR_BIT(P1IE, 3)
#define P14_Disable_DigitalInput CLR_BIT(P1IE, 4)
#define P15_Disable_DigitalInput CLR_BIT(P1IE, 5)
#define P16_Disable_DigitalInput CLR_BIT(P1IE, 6)
#define P17_Disable_DigitalInput CLR_BIT(P1IE, 7)
#define P30_Disable_DigitalInput CLR_BIT(P3IE, 0)
#define P31_Disable_DigitalInput CLR_BIT(P3IE, 1)
#define P32_Disable_DigitalInput CLR_BIT(P3IE, 2)
#define P33_Disable_DigitalInput CLR_BIT(P3IE, 3)
#define P34_Disable_DigitalInput CLR_BIT(P3IE, 4)
#define P35_Disable_DigitalInput CLR_BIT(P3IE, 5)
#define P36_Disable_DigitalInput CLR_BIT(P3IE, 6)
#define P37_Disable_DigitalInput CLR_BIT(P3IE, 7) |
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