PS3111 RDT结果貌似有一个新增

kkkkang · 发表于前天 16:35

求教
如上图，这个新增在哪片芯片上呀，我把它换一片其他的上去。
这是量产结果

************************************************************
Day: (30 \  4 \ 2025) Time: (16:31:47)  TesterNumber:1
************************************************************
[ConfigID]
ID=98 3C A5 93 7E D1-7DFL
[SN Set]
SN_Set=1
SN_Type=1
SN_Len=12
SN_Start=K0001
SN_End=K0009
SN_Mask=K0000
[Other]
SATA_SSC_Enable=1
[StationName]
01=EraseAll
02=RDT
03=RDTResult
04=MP
05=ReMP
06=ICT
07=UpdateFW
08=ScanBad
[InfoBlock_2]
Byte_290=E8
Byte_291=03
Byte_222=08
[General Info]
TestStationSel=3
TestStation=F1
WorkingNo=KW
ModelName=KW
SerialNum=K0001
MaxCurrent=400
[Flash Info]
Flh_Type=MLC_16K
Flh_MakeCode=Toshiba
Flh_ID=98 3c a5 93 7e d1
Flh_Capacity=524288
Flh_CapacitySel=0
Flh_Number=16
Flh_NumberSel=16
Flash Clock=200
Flash Interface=3
[Device Info]
SATASpeed=3
ControllerType=SSD-3111SB
ICFWVersion=SBFM01.3
3111SBISP_CodeVersion=M01.3
3111SBISP_MPBINCode=.\Bin\SBFM01.3.BIN
3111SBISP_RDTBINCode=.\Bin\SBSC01.1.BIN
SSD Size=2.5"
[Options]
DDRSize=32
Check_RDT_Table=1
Enable_Set_Custom_SMART_Temperature=1
Set_Custom_SMART_Temperature=35
Smart_Table=0
EnableSmartC3=1
SLCPoolSizeSel=6
SLCPoolSize=10485760
Disable_DIPM_Support=1
DEVSLP_Enable=1
Put_Thermal_Sensor=0
Skip_Check_RDDebugPage=1
PretestType=3
PMASetting=42035
Do_Hard_Bit_Retry_Test=1
EarlyBad_Spec=9999
SLCLaterBad_Spec=9999
SLCLaterBad_SpecPerPlane=9999
STL_LaterBad_Spec=9999
BTL_LaterBad_Spec=9999
LaterBad_Spec=9999
LaterBad_SpecPerPlane=9999
TotalBad_SpecPerDie=9999
TotalBad_SpecPerPlane=9999
Total_LaterBad_Spec=9999
TotalLaterBad_SpecPerDie=9999
TotalLaterBad_SpecPerPlane=9999
[EraseAll]
Do_Erase_First=0

[Log]
[ Success ] AES VUC Process OK.
[ Info ] MP AP: V2.06_x02(China), MAC Address: , ISP FW: SBFM01.3.BIN, Station:F1T
[ Success ] Check Device State OK.
[ Success ] Check IO State OK- Total take 0.034 sec.
   RDT FW : RDTC01.1
   RDT SDR start mark ok.
   RDT SDR end mark ok.
   RDT Flash start mark ok.
   CE_0 ReadRetryThreshold=0
   CE_1 ReadRetryThreshold=0
   CE_2 ReadRetryThreshold=0
   CE_3 ReadRetryThreshold=0
   CE_4 ReadRetryThreshold=0
   CE_5 ReadRetryThreshold=0
   CE_6 ReadRetryThreshold=0
   CE_7 ReadRetryThreshold=0
   CE_8 ReadRetryThreshold=0
   CE_9 ReadRetryThreshold=0
   CE_10 ReadRetryThreshold=0
   CE_11 ReadRetryThreshold=0
   CE_12 ReadRetryThreshold=0
   CE_13 ReadRetryThreshold=0
   CE_14 ReadRetryThreshold=0
   CE_15 ReadRetryThreshold=0
   RDT Flash end mark ok.
ScanBad: set_SSDSize= 0
(FW)Max_badblock_perplane = 64
Setting Early Bad SPEC = 9999
Read RDT Log:
[start]Total CE Number=16,Die per CE=2
Bad Block Log:
Fail Type,CE,Channel,plane,Physical block address,page number,Total Loop,Run Loop,Run Cycle,Step number,Stage number,Over threshold correctable bit,Time Stamp
(TLC/MLC loop, SLC loop, ECC threshold, SLC ECC threshold) = (1, 1, 40, 20):
(max later bad, max later bad per CE, max later bad per plane per CE, max erase fail, max program fail, max read fail, enable max fail) = (65535, 65535, 65535, 65535, 65535, 65535, 0):
  ……
Read correctable bit over threshold,7,0,1,0xa7d,32,2,0,0,0,Post Read,40,6862790
Setting Total Later Bad Spec Per Die : 9999
[total]CE_0,Die_0,Plane_0, All Bad= 12, Early Bad= 12, Later Bad= 0
[total]CE_0,Die_0,Plane_1, All Bad= 17, Early Bad= 17, Later Bad= 0
[total]CE_0,Die_0,Plane_2, All Bad= 8, Early Bad= 8, Later Bad= 0
[total]CE_0,Die_0,Plane_3, All Bad= 5, Early Bad= 5, Later Bad= 0
[total]CE_0,Die_1,Plane_0, All Bad= 4, Early Bad= 4, Later Bad= 0
[total]CE_0,Die_1,Plane_1, All Bad= 3, Early Bad= 3, Later Bad= 0
[total]CE_0,Die_1,Plane_2, All Bad= 2, Early Bad= 2, Later Bad= 0
[total]CE_0,Die_1,Plane_3, All Bad= 1, Early Bad= 1, Later Bad= 0
[total]CE_1,Die_0,Plane_0, All Bad= 13, Early Bad= 13, Later Bad= 0
[total]CE_1,Die_0,Plane_1, All Bad= 15, Early Bad= 15, Later Bad= 0
[total]CE_1,Die_0,Plane_2, All Bad= 12, Early Bad= 12, Later Bad= 0
[total]CE_1,Die_0,Plane_3, All Bad= 8, Early Bad= 8, Later Bad= 0
[total]CE_1,Die_1,Plane_0, All Bad= 3, Early Bad= 3, Later Bad= 0
[total]CE_1,Die_1,Plane_1, All Bad= 9, Early Bad= 9, Later Bad= 0
[total]CE_1,Die_1,Plane_2, All Bad= 3, Early Bad= 3, Later Bad= 0
[total]CE_1,Die_1,Plane_3, All Bad= 3, Early Bad= 3, Later Bad= 0
[total]CE_2,Die_0,Plane_0, All Bad= 5, Early Bad= 5, Later Bad= 0
[total]CE_2,Die_0,Plane_1, All Bad= 3, Early Bad= 3, Later Bad= 0
[total]CE_2,Die_0,Plane_2, All Bad= 5, Early Bad= 5, Later Bad= 0
[total]CE_2,Die_0,Plane_3, All Bad= 5, Early Bad= 5, Later Bad= 0
[total]CE_2,Die_1,Plane_0, All Bad= 11, Early Bad= 11, Later Bad= 0
[total]CE_2,Die_1,Plane_1, All Bad= 6, Early Bad= 6, Later Bad= 0
[total]CE_2,Die_1,Plane_2, All Bad= 2, Early Bad= 2, Later Bad= 0
[total]CE_2,Die_1,Plane_3, All Bad= 2, Early Bad= 2, Later Bad= 0
[total]CE_3,Die_0,Plane_0, All Bad= 13, Early Bad= 13, Later Bad= 0
[total]CE_3,Die_0,Plane_1, All Bad= 10, Early Bad= 10, Later Bad= 0
[total]CE_3,Die_0,Plane_2, All Bad= 4, Early Bad= 4, Later Bad= 0
[total]CE_3,Die_0,Plane_3, All Bad= 5, Early Bad= 5, Later Bad= 0
[total]CE_3,Die_1,Plane_0, All Bad= 6, Early Bad= 6, Later Bad= 0
[total]CE_3,Die_1,Plane_1, All Bad= 3, Early Bad= 3, Later Bad= 0
[total]CE_3,Die_1,Plane_2, All Bad= 4, Early Bad= 4, Later Bad= 0
[total]CE_3,Die_1,Plane_3, All Bad= 8, Early Bad= 8, Later Bad= 0
[total]CE_4,Die_0,Plane_0, All Bad= 8, Early Bad= 8, Later Bad= 0
[total]CE_4,Die_0,Plane_1, All Bad= 6, Early Bad= 6, Later Bad= 0
[total]CE_4,Die_0,Plane_2, All Bad= 5, Early Bad= 5, Later Bad= 0
[total]CE_4,Die_0,Plane_3, All Bad= 5, Early Bad= 5, Later Bad= 0
[total]CE_4,Die_1,Plane_0, All Bad= 8, Early Bad= 8, Later Bad= 0
[total]CE_4,Die_1,Plane_1, All Bad= 5, Early Bad= 5, Later Bad= 0
[total]CE_4,Die_1,Plane_2, All Bad= 1, Early Bad= 1, Later Bad= 0
[total]CE_4,Die_1,Plane_3, All Bad= 3, Early Bad= 3, Later Bad= 0
[total]CE_5,Die_0,Plane_0, All Bad= 6, Early Bad= 6, Later Bad= 0
[total]CE_5,Die_0,Plane_1, All Bad= 2, Early Bad= 2, Later Bad= 0
[total]CE_5,Die_0,Plane_2, All Bad= 2, Early Bad= 2, Later Bad= 0
[total]CE_5,Die_0,Plane_3, All Bad= 5, Early Bad= 5, Later Bad= 0
[total]CE_5,Die_1,Plane_0, All Bad= 23, Early Bad= 23, Later Bad= 0
[total]CE_5,Die_1,Plane_1, All Bad= 14, Early Bad= 14, Later Bad= 0
[total]CE_5,Die_1,Plane_2, All Bad= 16, Early Bad= 16, Later Bad= 0
[total]CE_5,Die_1,Plane_3, All Bad= 6, Early Bad= 6, Later Bad= 0
[total]CE_6,Die_0,Plane_0, All Bad= 19, Early Bad= 19, Later Bad= 0
[total]CE_6,Die_0,Plane_1, All Bad= 20, Early Bad= 20, Later Bad= 0
[total]CE_6,Die_0,Plane_2, All Bad= 20, Early Bad= 20, Later Bad= 0
[total]CE_6,Die_0,Plane_3, All Bad= 19, Early Bad= 19, Later Bad= 0
[total]CE_6,Die_1,Plane_0, All Bad= 16, Early Bad= 16, Later Bad= 0
[total]CE_6,Die_1,Plane_1, All Bad= 10, Early Bad= 10, Later Bad= 0
[total]CE_6,Die_1,Plane_2, All Bad= 11, Early Bad= 11, Later Bad= 0
[total]CE_6,Die_1,Plane_3, All Bad= 7, Early Bad= 7, Later Bad= 0
[total]CE_7,Die_0,Plane_0, All Bad= 28, Early Bad= 28, Later Bad= 0
[total]CE_7,Die_0,Plane_1, All Bad= 35, Early Bad= 34, Later Bad= 1
[total]CE_7,Die_0,Plane_2, All Bad= 28, Early Bad= 28, Later Bad= 0
[total]CE_7,Die_0,Plane_3, All Bad= 27, Early Bad= 27, Later Bad= 0
[total]CE_7,Die_1,Plane_0, All Bad= 4, Early Bad= 4, Later Bad= 0
[total]CE_7,Die_1,Plane_1, All Bad= 9, Early Bad= 9, Later Bad= 0
[total]CE_7,Die_1,Plane_2, All Bad= 3, Early Bad= 3, Later Bad= 0
[total]CE_7,Die_1,Plane_3, All Bad= 1, Early Bad= 1, Later Bad= 0
[total]CE_8,Die_0,Plane_0, All Bad= 21, Early Bad= 21, Later Bad= 0
[total]CE_8,Die_0,Plane_1, All Bad= 16, Early Bad= 16, Later Bad= 0
[total]CE_8,Die_0,Plane_2, All Bad= 14, Early Bad= 14, Later Bad= 0
[total]CE_8,Die_0,Plane_3, All Bad= 21, Early Bad= 21, Later Bad= 0
[total]CE_8,Die_1,Plane_0, All Bad= 4, Early Bad= 4, Later Bad= 0
[total]CE_8,Die_1,Plane_1, All Bad= 11, Early Bad= 11, Later Bad= 0
[total]CE_8,Die_1,Plane_2, All Bad= 7, Early Bad= 7, Later Bad= 0
[total]CE_8,Die_1,Plane_3, All Bad= 2, Early Bad= 2, Later Bad= 0
[total]CE_9,Die_0,Plane_0, All Bad= 5, Early Bad= 5, Later Bad= 0
[total]CE_9,Die_0,Plane_1, All Bad= 6, Early Bad= 6, Later Bad= 0
[total]CE_9,Die_0,Plane_2, All Bad= 3, Early Bad= 3, Later Bad= 0
[total]CE_9,Die_0,Plane_3, All Bad= 4, Early Bad= 4, Later Bad= 0
[total]CE_9,Die_1,Plane_0, All Bad= 21, Early Bad= 21, Later Bad= 0
[total]CE_9,Die_1,Plane_1, All Bad= 15, Early Bad= 15, Later Bad= 0
[total]CE_9,Die_1,Plane_2, All Bad= 14, Early Bad= 14, Later Bad= 0
[total]CE_9,Die_1,Plane_3, All Bad= 15, Early Bad= 15, Later Bad= 0
[total]CE_10,Die_0,Plane_0, All Bad= 29, Early Bad= 29, Later Bad= 0
[total]CE_10,Die_0,Plane_1, All Bad= 21, Early Bad= 21, Later Bad= 0
[total]CE_10,Die_0,Plane_2, All Bad= 10, Early Bad= 10, Later Bad= 0
[total]CE_10,Die_0,Plane_3, All Bad= 13, Early Bad= 13, Later Bad= 0
[total]CE_10,Die_1,Plane_0, All Bad= 15, Early Bad= 15, Later Bad= 0
[total]CE_10,Die_1,Plane_1, All Bad= 13, Early Bad= 13, Later Bad= 0
[total]CE_10,Die_1,Plane_2, All Bad= 9, Early Bad= 9, Later Bad= 0
[total]CE_10,Die_1,Plane_3, All Bad= 15, Early Bad= 15, Later Bad= 0
[total]CE_11,Die_0,Plane_0, All Bad= 35, Early Bad= 35, Later Bad= 0
[total]CE_11,Die_0,Plane_1, All Bad= 25, Early Bad= 25, Later Bad= 0
[total]CE_11,Die_0,Plane_2, All Bad= 44, Early Bad= 44, Later Bad= 0
[total]CE_11,Die_0,Plane_3, All Bad= 14, Early Bad= 14, Later Bad= 0
[total]CE_11,Die_1,Plane_0, All Bad= 21, Early Bad= 21, Later Bad= 0
[total]CE_11,Die_1,Plane_1, All Bad= 29, Early Bad= 29, Later Bad= 0
[total]CE_11,Die_1,Plane_2, All Bad= 12, Early Bad= 12, Later Bad= 0
[total]CE_11,Die_1,Plane_3, All Bad= 10, Early Bad= 10, Later Bad= 0
[total]CE_12,Die_0,Plane_0, All Bad= 12, Early Bad= 12, Later Bad= 0
[total]CE_12,Die_0,Plane_1, All Bad= 9, Early Bad= 9, Later Bad= 0
[total]CE_12,Die_0,Plane_2, All Bad= 11, Early Bad= 11, Later Bad= 0
[total]CE_12,Die_0,Plane_3, All Bad= 5, Early Bad= 5, Later Bad= 0
[total]CE_12,Die_1,Plane_0, All Bad= 6, Early Bad= 6, Later Bad= 0
[total]CE_12,Die_1,Plane_1, All Bad= 8, Early Bad= 8, Later Bad= 0
[total]CE_12,Die_1,Plane_2, All Bad= 4, Early Bad= 4, Later Bad= 0
[total]CE_12,Die_1,Plane_3, All Bad= 5, Early Bad= 5, Later Bad= 0
[total]CE_13,Die_0,Plane_0, All Bad= 9, Early Bad= 9, Later Bad= 0
[total]CE_13,Die_0,Plane_1, All Bad= 7, Early Bad= 7, Later Bad= 0
[total]CE_13,Die_0,Plane_2, All Bad= 7, Early Bad= 7, Later Bad= 0
[total]CE_13,Die_0,Plane_3, All Bad= 4, Early Bad= 4, Later Bad= 0
[total]CE_13,Die_1,Plane_0, All Bad= 5, Early Bad= 5, Later Bad= 0
[total]CE_13,Die_1,Plane_1, All Bad= 9, Early Bad= 9, Later Bad= 0
[total]CE_13,Die_1,Plane_2, All Bad= 6, Early Bad= 6, Later Bad= 0
[total]CE_13,Die_1,Plane_3, All Bad= 2, Early Bad= 2, Later Bad= 0
[total]CE_14,Die_0,Plane_0, All Bad= 7, Early Bad= 7, Later Bad= 0
[total]CE_14,Die_0,Plane_1, All Bad= 6, Early Bad= 6, Later Bad= 0
[total]CE_14,Die_0,Plane_2, All Bad= 10, Early Bad= 10, Later Bad= 0
[total]CE_14,Die_0,Plane_3, All Bad= 2, Early Bad= 2, Later Bad= 0
[total]CE_14,Die_1,Plane_0, All Bad= 12, Early Bad= 12, Later Bad= 0
[total]CE_14,Die_1,Plane_1, All Bad= 8, Early Bad= 8, Later Bad= 0
[total]CE_14,Die_1,Plane_2, All Bad= 7, Early Bad= 7, Later Bad= 0
[total]CE_14,Die_1,Plane_3, All Bad= 3, Early Bad= 3, Later Bad= 0
[total]CE_15,Die_0,Plane_0, All Bad= 12, Early Bad= 12, Later Bad= 0
[total]CE_15,Die_0,Plane_1, All Bad= 17, Early Bad= 17, Later Bad= 0
[total]CE_15,Die_0,Plane_2, All Bad= 11, Early Bad= 11, Later Bad= 0
[total]CE_15,Die_0,Plane_3, All Bad= 6, Early Bad= 6, Later Bad= 0
[total]CE_15,Die_1,Plane_0, All Bad= 8, Early Bad= 8, Later Bad= 0
[total]CE_15,Die_1,Plane_1, All Bad= 4, Early Bad= 4, Later Bad= 0
[total]CE_15,Die_1,Plane_2, All Bad= 2, Early Bad= 2, Later Bad= 0
[total]CE_15,Die_1,Plane_3, All Bad= 3, Early Bad= 3, Later Bad= 0
MaxCycle:2 FlashNum:16 BlocksPerDie:2 BlockDevide:8192
[Total LaterBad Per Die]
Cycle_0 CE_0 Die_0 : 0
Cycle_0 CE_0 Die_1 : 0
Cycle_0 CE_1 Die_0 : 0
Cycle_0 CE_1 Die_1 : 0
Cycle_0 CE_2 Die_0 : 0
Cycle_0 CE_2 Die_1 : 0
Cycle_0 CE_3 Die_0 : 0
Cycle_0 CE_3 Die_1 : 0
Cycle_0 CE_4 Die_0 : 0
Cycle_0 CE_4 Die_1 : 0
Cycle_0 CE_5 Die_0 : 0
Cycle_0 CE_5 Die_1 : 0
Cycle_0 CE_6 Die_0 : 0
Cycle_0 CE_6 Die_1 : 0
Cycle_0 CE_7 Die_0 : 1
Cycle_0 CE_7 Die_1 : 0
Cycle_0 CE_8 Die_0 : 0
Cycle_0 CE_8 Die_1 : 0
Cycle_0 CE_9 Die_0 : 0
Cycle_0 CE_9 Die_1 : 0
Cycle_0 CE_10 Die_0 : 0
Cycle_0 CE_10 Die_1 : 0
Cycle_0 CE_11 Die_0 : 0
Cycle_0 CE_11 Die_1 : 0
Cycle_0 CE_12 Die_0 : 0
Cycle_0 CE_12 Die_1 : 0
Cycle_0 CE_13 Die_0 : 0
Cycle_0 CE_13 Die_1 : 0
Cycle_0 CE_14 Die_0 : 0
Cycle_0 CE_14 Die_1 : 0
Cycle_0 CE_15 Die_0 : 0
Cycle_0 CE_15 Die_1 : 0
Cycle_1 CE_0 Die_0 : 0
Cycle_1 CE_0 Die_1 : 0
Cycle_1 CE_1 Die_0 : 0
Cycle_1 CE_1 Die_1 : 0
Cycle_1 CE_2 Die_0 : 0
Cycle_1 CE_2 Die_1 : 0
Cycle_1 CE_3 Die_0 : 0
Cycle_1 CE_3 Die_1 : 0
Cycle_1 CE_4 Die_0 : 0
Cycle_1 CE_4 Die_1 : 0
Cycle_1 CE_5 Die_0 : 0
Cycle_1 CE_5 Die_1 : 0
Cycle_1 CE_6 Die_0 : 0
Cycle_1 CE_6 Die_1 : 0
Cycle_1 CE_7 Die_0 : 0
Cycle_1 CE_7 Die_1 : 0
Cycle_1 CE_8 Die_0 : 0
Cycle_1 CE_8 Die_1 : 0
Cycle_1 CE_9 Die_0 : 0
Cycle_1 CE_9 Die_1 : 0
Cycle_1 CE_10 Die_0 : 0
Cycle_1 CE_10 Die_1 : 0
Cycle_1 CE_11 Die_0 : 0
Cycle_1 CE_11 Die_1 : 0
Cycle_1 CE_12 Die_0 : 0
Cycle_1 CE_12 Die_1 : 0
Cycle_1 CE_13 Die_0 : 0
Cycle_1 CE_13 Die_1 : 0
Cycle_1 CE_14 Die_0 : 0
Cycle_1 CE_14 Die_1 : 0
Cycle_1 CE_15 Die_0 : 0
Cycle_1 CE_15 Die_1 : 0

DDR Log:
Cycle,Step,Temp,Results,Time(ms)
255,8,40,SDR Test PASS,255
0,8,40,SDR Test PASS,5335
1,8,50,SDR Test PASS,86089
2,8,40,SDR Test PASS,25414
3,8,40,SDR Test PASS,17101
4,8,40,SDR Test PASS,9184
255,8,40,SDR Test PASS,255
32,8,40,SDR Test PASS,5564
33,8,50,SDR Test PASS,207197
34,8,40,SDR Test PASS,25521
35,8,40,SDR Test PASS,17461
36,8,40,SDR Test PASS,9419
255,8,40,SDR Test PASS,255
64,8,50,SDR Test PASS,5163
65,8,50,SDR Test PASS,79357
66,8,40,SDR Test PASS,25844
67,8,40,SDR Test PASS,27430
68,8,40,SDR Test PASS,1
255,8,40,SDR Test PASS,255
96,8,40,SDR Test PASS,827
97,8,50,SDR Test PASS,12011
98,8,40,SDR Test PASS,21950
99,8,40,SDR Test PASS,20617
100,8,40,SDR Test PASS,0
255,8,40,SDR Test PASS,255
128,8,40,SDR Test PASS,117649
255,8,40,SDR Test PASS,255
160,8,40,SRAM Test PASS,18306
161,8,40,SRAM Test PASS,4727
162,8,40,SRAM Test PASS,1885
163,8,40,SRAM Test PASS,6053
164,8,40,SRAM Test PASS,342
165,15,40,SRAM Test PASS,343
      SDR testing time= 752 seconds
SDRLog Sector = 4 TempLog Sector = 8
Temperature_Time Log:
Cycle,Step,Temp1,Temp2,Temp3,Temp4,Temp5,Temp6,Time(ms)
1,0,60,60,60,60,60,60,8439377
1,0,60,60,60,60,60,60,12689645
2,0,60,60,60,60,60,60,14904845
2,0,60,60,60,60,60,60,17122861
      Flash testing time= 17122 seconds

Self_BurnIn Total testing time= 4:57:55
[ Success ] [end]Read RDT Log ok.
[ Success ] Read RDT Log, Total take(sec): 3.020 sec.
[ End ] Time: (16:31:50)